Phase-locked loops (PLLs) are a common circuit block implemented within various electrical systems. Providing the ability to generate output frequencies in multiples of a fixed reference frequency, PLLs are widely used in telecommunication circuits, radio systems, and microprocessors, as well as other electronic systems. The output signal from the PLL, for example, can be provided to various types of circuits to implement clock recovery circuits, frequency synthesis circuits whether for modulators and/or de-modulators, on-board system clocks, clock distribution circuits, and various other circuits that generate or rely upon a frequency controlled signal.
In general, PLLs are composed of four blocks. These blocks include a voltage controlled oscillator (VCO), a phase frequency detector (PFD), a loop filter, and a closed loop negative feedback path from the VCO to the PFD. Typically, the PFD compares a phase and frequency of a feedback signal output from the VCO with a fixed frequency reference signal provided to the PLL. The PFD and loop filter convert the frequency and phase differences between the feedback VCO signal and the fixed frequency reference signal to an output voltage. The output voltage can then be used to control the frequency of the signal output from the VCO. Using phase and frequency error information, the PFD adjusts the control voltage of the VCO, thereby changing the frequency of the signal output from the VCO until the phase and frequency of the VCO output signal and the reference clock signal are matched.
There are a variety of design issues to consider when implementing a PLL. PLL startup time and PLL stability are often important aspects of a PLL design, particularly since PLLs are closed loop feedback systems. The importance of any individual PLL design parameter will likely vary according to the particular application in which the PLL is used. As such, the PLL often must meet stringent performance parameters, e.g., output frequency, noise and jitter specifications, spur reduction, and the like, for effective operation within the larger system. Each block of the PLL is often constrained to operate within a particular range to ensure acceptable performance of the PLL as a whole.
The interdependence among design parameters of the PLL can complicate the development of a successful PLL design. Performance improvement in a particular parameter of the PLL design, e.g., to improve startup time or stability, often leads to performance degradation in one or more other aspects of the PLL design. In many cases, it becomes necessary to prioritize parameters, sacrificing performance in one design parameter to meet a performance requirement for another design parameter of greater importance.